SOI technology consists in separating a fine silicon layer (a few nanometers) on a silicon substrate by a relatively thick insulator layer (a few tens of nanometers, as a general rule).
Integrated circuits produced with SOI technology exhibit certain advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits also induce lower parasitic capacitances, which make it possible to improve switching speed. Moreover, the phenomenon of parasitic triggering (known as “latchup”) encountered by Bulk-technology MOS transistors can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC or MEMS type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and thus turn out to be more reliable in applications where such radiations may induce operating problems, in particular in space applications. SOI integrated circuits may in particular comprise random-access memories of SRAM type or logic gates.
The reduction in the static consumption of logic gates while increasing their tripping speed forms the subject of much research. Certain integrated circuits under development integrate logic gates with low consumption and also logic gates with high tripping speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage of certain transistors of the logic gates with fast access is lowered, and the threshold voltage of other transistors of the logic gates with low consumption is increased. In Bulk technology, the modulation of the threshold voltage level of transistors of the same type is performed by differentiating their channel doping level. However, in FDSOI (for Fully Depleted Silicon On Insulator) technology, the doping of the channel is almost zero (1015 cm−3). Thus, the doping level of the channel of the transistors therefore cannot exhibit significant variations, thus preventing differentiation of the threshold voltages in this manner. A solution proposed in certain studies for producing transistors of the same type with distinct threshold voltages is to integrate various gate materials for these transistors. However, the practical production of such an integrated circuit turns out to be technically tricky and economically prohibitive.
In order to have distinct threshold voltages for various transistors in FDSOI technology, it is also known to use a back gate or a biased ground plane disposed between a thin insulating oxide layer (TBOX or UTBOX) and the silicon substrate. By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the various transistors. It will thus be possible to have low-threshold-voltage transistors termed LVT (for “Low Vt”, typically 400 mV), high-threshold-voltage transistors termed HVT (for “High Vt”, typically 550 mV) and medium-threshold-voltage transistors termed SVT (for “Standard Vt”, typically 450 mV).
Various designs have been developed in order to optimize the electrostatic control of the channel of such transistors (quantified in particular by the values DIBL (for drain-induced barrier lowering) and without SS (for subthreshold swing)).
According to a first design entitled 3DFDSOI, the channel exhibits a width that is greater than its thickness (dimension according to the perpendicular to the insulating oxide layer) and the gate envelops the lateral faces and also the upper face of the channel.
According to a second design known by the term “Tri Gate,” the channel exhibits a width that is roughly equivalent to its thickness and the gate envelops the lateral faces and also the upper face of the channel. Overall it is considered that the number of gates acting on the channel is multiplied.
According to a third design known by the term “FinFET,” the channel exhibits a width that is less than its thickness and the gate envelops the lateral faces and also the upper face of the channel.
The general aim of these designs is to maximize the coverage of the channel by the gate. Among these designs, it is generally considered that the higher the ratio of the thickness to the width of the channel:                the more a high electrostatic control of the channel is obtained;        the more complex the method of fabrication of the transistor;        the more the method of fabrication of the transistor comprises dispersions in the channel width and in the threshold voltage; and        the less the threshold voltage of the transistor can be adapted by biasing its back gate.        
Thus, with a design of the FinFET type, it turns out to be particularly tricky to produce integrated circuits comprising transistors having different threshold voltages or dynamically configurable threshold voltages. It is in particular tricky to compensate the dispersions of the threshold voltage by biasing the back gate.